The F100L Instruction Set¶
The following pages present complete descriptions for all instructions implemented in the F100L.
Instruction Encoding¶
All instruction encodings are defined as overlapping but mutually exclusive bit fields.
The bit fields are defined as follows
Field
Number of bits
Bit positions
Comment
F
4
15..12
Instruction class or function
I
1
11
Address Mode
T
2
11,10
General field to qualify F=0 instructions
R
2
9,8
Register field or autoindex mode for indirect addressing
S
2
7,6
General field to qualify F=0 instructions
J
2
5,4
General field to qualify F=0 instructions
N
11
10..0
Memory address for direct addressing
P
8
7..0
Memory address used as pointer for pointer indirect addressing
B
4
3..0
Shift number or bit significance
Where a don’t care (x) bit is presented in the tables, the assembler will consistently use a ‘0’. The emulator will ignore this field during decoding.
Instruction Timings¶
All instruction timings are defined using the following definitions
Ra1 = Program memory read access time
Ra2 = Data memory read access time
Rc1 = Program memory read cycle time
Rc2 = Data memory read cycle time
M = Readmodifywrite cycle time
Wc = Data memory write cycle time
L = 1 Logic cycle time (2x period of the CPU clock input)
Abbreviations¶
Definitions
N 11 bit memory address (associated with opcode field N above)
P 8 bit memory address (associated with opcode field P above)
W 15 bit memory address
D 16 bit immediate data
(N) Contents of memory location N
(P) Contents of memory location P
(W) Contents of memory location W
PC Value of the Program Counter (when pointing at the opcode word)
(PC+d) Contents of memory location offset by d words from the opcode
Instruction Set Summary¶
Opcode 
Comment 
Addressing Modes 
Parameters 
MultiWord Operation 

Implicit 
N 
,D 
/P 
/P+ 
/P 
.W 
B A 
B CR 
B W 

ADD 
Add (with carry) 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

ADS 
Add (with carry), store to memory 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

AND 
Logical AND 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

CAL 
Call Subroutine 
✓ 
✓ 
✓ 
✓ 

CLR 
Bit Manipulation 
✓ 
✓ 
✓ 

CMP 
Compare 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

HALT 
Stop Processor Execution 
✓ 
✓ 

ICZ 
Increment and Jump if NonZero 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

JBC 
Conditional Jump 
✓ 
✓ 
✓ 

JBS 
Conditional Jump 
✓ 
✓ 
✓ 

JCS 
Conditional Jump 
✓ 
✓ 
✓ 

JMP 
Unconditional Jump 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

JSC 
Conditional Jump 
✓ 
✓ 
✓ 

LDA 
Load Accumulator from memory 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

NEQ 
Logical XOR 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

RTC 
Return from Subroutine 
✓ 

RTN 
Return from Subroutine 
✓ 

SBS 
Subtract (with carry), store to memory 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

SET 
Bit Manipulation 
✓ 
✓ 
✓ 

SJM 
Switch Jump 

SLA 
Shift Left Arithmetic 
✓ 
✓ 
✓ 
✓ 

SLE 
Rotate Left 
✓ 
✓ 
✓ 

SLL 
Shift Left Logical 
✓ 
✓ 
✓ 
✓ 

SRA 
Shift Right Arithmetic 
✓ 
✓ 
✓ 
✓ 

SRE 
Rotate Right 
✓ 
✓ 
✓ 

SRL 
Shift Right Logical 
✓ 
✓ 
✓ 
✓ 

STO 
Store Accumulator to Memory 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 

SUB 
Subtract (with carry) 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 
✓ 
Instruction Definitions¶
ADD  Add (With Carry)¶
Perform addition of the accumulator and an operand with the result being stored in the accumulator.
When the multilength ‘M’ flag is set, the carry bit from a previous operation is included in the addition.
Function
When ‘M’ is clear
ADD N A < (N) + A
ADD ,D A < D + A
ADD /P A < (P) + A
ADD /P+ P < P + 1 ; A < (P) + A
ADD /P A < (P) + A ; P < P  1
ADD .W A < (W) + A
When ‘M’ is set
ADD N A < (N) + A + C
ADD ,D A < D + A + C
ADD /P A < (P) + A + C
ADD /P+ P < P + 1 ; A < (P)  A + C
ADD /P A < (P) + A + C ; P < P  1
ADD .W A < (W) + A + C
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

1001 
0 
11’b<nonzero addr> 
none 
ADD N 
TBC 

1001 
0 
11’b000000000000 
16`b<data> 
ADD ,D 
TBC 

1001 
1 
x 
x0 
8’b<nonzero ptr> 
none 
ADD /P 
TBC 

1001 
1 
x 
01 
8’b<nonzero ptr> 
none 
ADD /P+ 
TBC 

1001 
1 
x 
11 
8’b<nonzero ptr> 
none 
ADD /P 
TBC 

1001 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
ADD .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
C is set if the operation results in a carry out, otherwise cleared
Z is set if the result is allzeroes, otherwise cleared
S is set if the MSB of the result is a ‘1’, otherwise cleared
V is set if the addition of two numbers with the same sign results in a value with the opposite sign
ADS  Add (With Carry), Store to Memory¶
Perform addition of the accumulator and an operand with the result being stored in the operand’s original location.
When the multilength ‘M’ flag is set, the carry bit from a previous operation is included in the addition.
Function
When ‘M’ is clear
ADS N (N) < (N) + A
ADS ,D (PC+1) < D + A
ADS /P (P) < (P) + A
ADS /P+ P < P + 1 ; (P) < (P) + A
ADS /P (P) < (P) + A ; P < P  1
ADS .W (W) < (W) + A
When ‘M’ is set
ADS N (N) < (N) + A + C
ADS ,D (PC+1) < D + A + C
ADS /P (P) < (P) + A + C
ADS /P+ P < P + 1 ; (P) < (P)  A + C
ADS /P (P) < (P) + A + C ; P < P  1
ADS .W (W) < (W) + A + C
In the immediate mode operation, data ‘D’ is taken from the location (PC+1), ie the word immediately after the opcode, and the the result is returned to that location.
The result of the addition passes through the Operand Register as it is written back to memory.
The accumulator is left unchanged by the result of the ADS operation.
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

0101 
0 
11’b<nonzero addr> 
none 
ADS N 
TBC 

0101 
0 
11’b000000000000 
16’b<data> 
ADS ,D 
TBC 

0101 
1 
x 
x0 
8’b<nonzero ptr> 
none 
ADS /P 
TBC 

0101 
1 
x 
01 
8’b<nonzero ptr> 
none 
ADS /P+ 
TBC 

0101 
1 
x 
11 
8’b<nonzero ptr> 
none 
ADS /P 
TBC 

0101 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
ADS .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
C is set if the operation results in a carry out, otherwise cleared
Z is set if the result is allzeroes, otherwise cleared
S is set if the MSB of the result is a ‘1’, otherwise cleared
V is set if the addition of two numbers with the same sign results in a value with the opposite sign
AND  Logical AND¶
Perform a bitwise logical AND of accumulator with the specified operand.
Function
AND N A < A & (N)
AND ,D A < A & D
AND /P A < A & (P)
AND /P+ P < P + 1 ; A < A & (P)
AND /P A < A & (P) ; P < P  1
AND .W A < A & (W)
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R  P 

1100 
0 
11’b<nonzero addr> 
none 
AND N 
Ra1 + Ra2 + 18L 

1100 
0 
11’b000000000000 
16’b<data> 
AND ,D 
Ra1 + Rc1 + 18L 

1100 
1 
x 
x0 
8’b<nonzero ptr> 
none 
AND /P 
Ra1 + Ra2 + 18L 

1100 
1 
x 
01 
8’b<nonzero ptr> 
none 
AND /P+ 
Ra1 + M + 34L 

1100 
1 
x 
11 
8’b<nonzero ptr> 
none 
AND /P 
Ra1 + M + 34L 

1100 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
AND .W 
Ra1 + Ra2 + Rc1 + 18L 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
1 
x 
 
C is always set to 1
Z is set if the result is allzeroes, otherwise cleared
S is set if the MSB of the result is a ‘1’, otherwise cleared
V is undefined after this operation
CAL  Call Subroutine¶
Jump to subroutine location provided by operand, storing return address in the link stack
Function
CAL N (LSP+1) < PC+1; (LSP+2) < CR ; PC < N; LSP < LSP+2
CAL ,D (LSP+1) < PC+1; (LSP+2) < CR ; PC < PC+1; LSP < LSP+2
CAL /P (LSP+1) < PC+1; (LSP+2) < CR ; PC < (P); LSP < LSP+2
CAL .W (LSP+1) < PC+2; (LSP+2) < CR ; PC < W; LSP < LSP+2
Where LSP is link stack pointer held in memory location 0.
NOTE: on entry the link stack pointer must always be an odd number.
CAL ,D is a special case where only the link is stored in the link stack and the ‘D’ operand is treated as the next instruction. In this form the assembler discards the operand.
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

0010 
0 
11’b<nonzero addr> 
none 
CAL N 
TBC 

0010 
0 
11’b000000000000 
none 
CAL ,D 
TBC 

0010 
1 
x 
xx 
8’b<nonzero ptr> 
none 
CAL /P 
TBC 

0010 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
CAL .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 







M is always cleared by this operation
CLR, SET  Bit manipulation¶
Clear or set a single bit within the operand.
Function
CLR B A A[B] < 0
CLR B CR CR[B] < 0
CLR B W (W)[B] < 0
SET B A A[B] < 1
SET B CR CR[B] < 1
CLR B W (W)[B] < 1
Instruction Encoding
Opcode Word 
Operand 
Function 
Cycle count 

F 
T 
R 
S 
J 
B 

0000 
00 
x0 
11 
11 
4’b<bit field> 
none 
CLR B A 
TBC 

0000 
00 
01 
11 
11 
4’b<bit field> 
none 
CLR B CR 
TBC 

0000 
00 
11 
11 
11 
4’b<bit field> 
x 
15’b<address W> 
CLR B W 
TBC 
0000 
00 
x0 
11 
10 
4’b<bit field> 
none 
SET B A 
TBC 

0000 
00 
01 
11 
10 
4’b<bit field> 
none 
SET B CR 
TBC 

0000 
00 
11 
11 
10 
4’b<bit field> 
x 
15’b<address W> 
SET B W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
 
 
 
 
Note that any operation on the CR will set the selected bit, but otherwise the Condition Register is not affected by these instructions.
CMP  Compare¶
Perform either a single or multilength comparison of the accumulator and an operand, depending on the state of the multilength flag ‘M’ in the condition register.
When M is set, a sequence of these instructions performs a multilength subtraction without overwriting any of the operands. Multilength compare is performed by including the carry from a previous compare in at the LSB end of the current instruction
For both single and multilength comparisons the results are discarded but the appropriate flags are set in the condition register.
The ‘M’ flag is always set at the end of this operation.
Function
When ‘M’ is clear, single length comparison
CMP N x < (N)  A
CMP ,D x < D  A
CMP /P x < (P)  A
CMP /P+ P < P + 1 ; x < (P)  A
CMP /P x < (P)  A ; P < P  1 ;
CMP .W x < (W)  A
When ‘M’ is set
CMP N x < (N)  A + C  1
CMP ,D x < D  A + C  1
CMP /P x < (P)  A + C  1
CMP /P+ P < P + 1 ; x < (P)  A + C  1
CMP /P x < (P)  A + C  1; P < P  1 ;
CMP .W x < (W)  A + C  1
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 

R 
P 

1011 
0 
11’b<nonzero addr> 
none 
CMP N 
TBC 

1011 
0 
11’b000000000000 
16’b<data> 
CMP ,D 
TBC 

1011 
1 
x 
x0 
8’b<nonzero ptr> 
none 
CMP /P 
TBC 

1011 
1 
x 
01 
8’b<nonzero ptr> 
none 
CMP /P+ 
TBC 

1011 
1 
x 
11 
8’b<nonzero ptr> 
none 
CMP /P 
TBC 

1011 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
CMP .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
1 
 
C is cleared if the operation results in a borrow (carry), otherwise set
M is always set to 1
Z is set if the result is allzeroes, otherwise cleared
S is set if the MSB of the result is a ‘1’, otherwise cleared
V is set if the subtraction of two numbers of different sign results in a number with the same sign as the subtrahend, otherwise cleared
HALT  Stop Processor Execution¶
This instruction stops the CPU and prevents the F100L from executing any further instructions.
Once stopped the CPU can only be restarted by driving the RUN* pin high (the ‘STOP’ state) and then low again.
The least significant 10 bits of the Opcode are ignored by the processor but can be used by the programmer to provide a halt number. The assembler allows the HALT instruction to appear either with or without an operand and in the latter case the 10 LSBs will be encoded into the opcode.
HALT Stop processor execution
HALT ,D Stop processor execution
Instruction Encoding
Opcode Word 
Function 
Cycle count 

F 
T 
Halt Number 

0000 
01 
10’b<Halt Number> 
HALT 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
 
 
 
 
The condition register is unaffected by this instruction
ICZ  Increment and Jump if NonZero¶
Increment the contents of a counter or address and jump to a specified location if the result is nonzero
Function
ICZ N W1 (N) < (N)+1 ; if (Z==0) PC < W1
ICZ ,D W1 D < D+1 ; if (Z==0) PC < W1
ICZ /P W1 (P) <= (P)+1 ; if (Z==0) PC < W1
ICZ /P+ W1 P < P+1 ; (P) < (P)+1 ; if (Z==0) PC < W1
ICZ /P W1 (P) < (P)+1 ; P < P1; ; if (Z==0) PC < W1
ICZ .W W1 (W) < (W)+1 ; if (Z==0) PC < W1
The Operand Register holds the value written back to memory at the end of the instruction, but the contents of the accumulator are preserved.
Instruction Encoding
Opcode Word 
Operand Word 
Second Operand 
Function 
Cycle count 

F 
I 
N 

R 
P 

0111 
0 
11’b<nonzero addr> 
x 
15’b<jump addr> 
none 
ICZ N W1 
TBC 

0111 
0 
11’b000000000000 
16’b<data> 
x 
15’b<jump addr> 
ICZ ,D W1 
TBC 

0111 
1 
x 
x0 
8’b<nonzero ptr> 
x 
15’b<jump addr> 
none 
ICZ /P W1 
TBC 

0111 
1 
x 
01 
8’b<nonzero ptr> 
x 
15’b<jump addr> 
none 
ICZ /P+ W1 
TBC 

0111 
1 
x 
11 
8’b<nonzero ptr> 
x 
15’b<jump addr> 
none 
ICZ /P W1 
TBC 

0111 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
x 
15’b<jump addr>x 
ICZ .W W1 
TBC 
Condition Register*
F 
M 
C 
S 
V 
Z 
I 
 
 
 
 
 
 
 
The condition code register is unchanged after this operation
JBC, JBS, JCS, JSC  Conditional Jump¶
These instructions inspect a bit field in the first operand and if the expected condition is satisfied jump to the location specified in the second operand.
JBC (Jump bit clear) will jump to the specified destination if the inspected bit is clear (0).
JCS extends this operation to set the specified bit after the jump has been made.
JBS (Jump bit set) will jump to the specified destination if the inspected bit is set (1).
JSC extends this operation to clear the specified bit after the jump has been made.
Each instruction can specify the bit to be located in one of
the Accumulator (A),
the Condition Register (CR), or
a memory location (W)
Function
JBC B A W1 if (A[B] == 0) PC < W1
JBC B CR W1 if (CR[B] == 0) PC < W1
JBC B W W1 if ((W)[B] == 0) PC < W1
JBS B A W1 if (A[B] == 1) PC < W1
JBS B CR W1 if (CR[B] == 1) PC < W1
JBS B W W1 if ((W)[B] == 1) PC < W1
JCS B A W1 if (A[B] == 0) PC < W1 ; A[B] < 1
JCS B CR W1 if (CR[B] == 0) PC < W1 ; CR[B] < 1
JCS B W W1 if ((W)[B] == 0) PC < W1 ; (W)[B] < 1
JSC B A W1 if (A[B] == 1) PC < W1 ; A[B] < 0
JSC B CR W1 if (CR[B] == 1) PC < W1 ; CR[B] < 0
JSC B W W1 if ((W)[B] == 1) PC < W1 ; (W)[B] < 0
Instruction Encoding
Opcode Word 
Operand 
Operand 
Function 
Cycle count 

F 
T 
R 
S 
J 
B 

0000 
0 
x0 
10 
00 
4’b<bit field> 
x 
15’b<address W1> 
none 
JBC B A W1 
TBC 

0000 
0 
01 
10 
00 
4’b<bit field> 
x 
15’b<address W1> 
none 
JBC B CR W1 
TBC 

0000 
0 
11 
10 
00 
4’b<bit field> 
x 
15’b<address W> 
x 
15’b<address W1> 
JBC B W W1 
TBC 

0000 
0 
x0 
10 
01 
4’b<bit field> 
x 
15’b<address W1> 
none 
JBS B A W1 
TBC 

0000 
0 
01 
10 
01 
4’b<bit field> 
x 
15’b<address W1> 
none 
JBS B CR W1 
TBC 

0000 
0 
11 
10 
01 
4’b<bit field> 
x 
15’b<address W> 
x 
15’b<address W1> 
JBS B W W1 
TBC 

0000 
0 
x0 
10 
10 
4’b<bit field> 
x 
15’b<address W1> 
none 
JCS B A W1 
TBC 

0000 
0 
01 
10 
10 
4’b<bit field> 
x 
15’b<address W1> 
none 
JCS B CR W1 
TBC 

0000 
0 
11 
10 
10 
4’b<bit field> 
x 
15’b<address W> 
x 
15’b<address W1> 
JCS B W W1 
TBC 

0000 
0 
x0 
10 
11 
4’b<bit field> 
x 
15’b<address W1> 
none 
JSC B A W1 
TBC 

0000 
0 
01 
10 
11 
4’b<bit field> 
x 
15’b<address W1> 
none 
JSC B CR W1 
TBC 

0000 
0 
11 
10 
11 
4’b<bit field> 
x 
15’b<address W> 
x 
15’b<address W1> 
JSC B W W1 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
 
 
 
 
The condition bits are not evaluated during this instruction, but any bits explicitly set or cleared when using the condition register as the first operand will affect the relevant flag.
JMP  Unconditional Jump¶
Unconditional jump to the location provided by the operand.
Function
JMP N PC < N
JMP ,D PC < PC + 1
JMP /P PC < (P)
JMP /P+ P < P+1 ; PC < (P)
JMP /P PC < (P) ; P < P  1
JMP .W PC < W
Note that the JMP,D form causes no branching and instruction proceeds to execute the next word (the ‘D’ effectively) as the next instruction. This instruction is effectively a NOP. The assembler discards the literal provided when using this form so that the next assembled instruction will be executed.
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

1111 
0 
11’b<nonzero addr> 
none 
JMP N 
TBC 

1111 
0 
11’b000000000000 
none 
JMP ,D 
TBC 

1111 
1 
x 
x0 
8’b<nonzero ptr> 
none 
JMP /P 
TBC 

1111 
1 
x 
01 
8’b<nonzero ptr> 
none 
JMP /P+ 
TBC 

1111 
1 
x 
11 
8’b<nonzero ptr> 
none 
JMP /P 
TBC 

1111 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
JMP .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
 
 
 
 
The condition register is not affected by this instruction
LDA  Load Accumulator from Memory¶
Load the accumulator with a value from the specified memory location
Function
LDA N A < (N)
LDA ,D A < D
LDA /P A < (P)
LDA /P+ P < P + 1 ; A < (P)
LDA /P A < (P) ; P < P  1
LDA .W A < (W)
The operand register (OR) will have the same value as the accumulator at the end of this instruction.
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

1000 
0 
11`b<nonzero addr> 
none 
LDA N 
TBC 

1000 
0 
11`b000000000000 
16`b<data> 
LDA ,D 
TBC 

1000 
1 
x 
x0 
8`b<nonzero ptr> 
none 
LDA /P 
TBC 

1000 
1 
x 
01 
8`b<nonzero ptr> 
none 
LDA /P+ 
TBC 

1000 
1 
x 
11 
8`b<nonzero ptr> 
none 
LDA /P 
TBC 

1000 
1 
x 
xx 
8`b00000000 
x 
15`b<addr> 
LDA .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
0 
 
Z is set if the new accumulator value is allzeroes, otherwise cleared
S is set if the MSB of the new accumulator value is a ‘1’, otherwise cleared
V is always cleared
NEQ  Logical XOR¶
Perform a bitwise logical exclusiveOR of the Accumulator and specified operand.
Function
NEQ N A < A ^ (N)
NEQ ,D A < A ^ D
NEQ /P A < A ^ (P)
NEQ /P+ P < P + 1 ; A < A ^ (P)
NEQ /P A < A ^ (P) ; P < P  1
NEQ .W A < A ^ (W)
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

1101 
0 
11’b<nonzero addr> 
none 
NEQ N 
Ra1 + Ra2 + 18L 

1101 
0 
11’b000000000000 
16’b<data> 
NEQ ,D 
Ra1 + Rc1 + 18L 

1101 
1 
x 
x0 
8’b<nonzero ptr> 
none 
NEQ /P 
Ra1 + Ra2 + 18L 

1101 
1 
x 
01 
8’b<nonzero ptr> 
none 
NEQ /P+ 
Ra1 + M + 34L 

1101 
1 
x 
11 
8’b<nonzero ptr> 
none 
NEQ /P 
Ra1 + M + 34L 

1101 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
NEQ .W 
Ra1 + Ra2 + Rc1 + 18L 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
0 
x 
 
C is always reset to 0
Z is set if the result is allzeroes, otherwise cleared
S is set if the MSB of the result is a ‘1’, otherwise cleared
V is undefined after this operation
RTN, RTC  Return from Subroutine¶
These instructions perform a return from subroutine operation.
RTN restores bits 05 of the Condition Register from the word pointed to by the link stack pointer (location 0). The link stack pointer is then decremented to point to the return address, and this is placed into the program counter. The link stack pointer is then decremented again to finish the instruction pointing to the last valid stack entry.
RTC operates in a similar manner but discards the Condition Register entry from the stack.
NOTE: on entry the link stack pointer must always be an odd number.
Function
RTN CR[5:0] < (LSP)[5:0] ; LSP < LSP1 ; PC < (LSP) ; LSP < LSP  1
RTC PC < (LSP1) ; LSP < LSP  2
Where LSP = Link Stack Pointer which is always held in location 0 in memory
Instruction Encoding
Opcode Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

0011 
0 
11’bxxxxxxxxxxx 
RTN 
TBC 

0011 
1 
11’bxxxxxxxxxxx 
RTC 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
Instruction 
 
RTN 

 
 
 
 
 
 
 
RTC 
Bit 6, the Fail flag entry, is not overwritten by either of these instructions.
SBS  Subtract (With Carry), Store to Memory¶
Perform substraction of the accumulator from the value of an operand with the result being stored in the operand’s original location.
When the multilength ‘M’ flag is set, the carry bit from a previous operation is included in the subtraction.
Function
When M is clear, perform a simple subtraction
SBS N (N) < (N)  A
SBS ,D (PC+1) < D  A
SBS /P (P) < (P)  A
SBS /P+ P < P + 1 ; (P) < (P)  A
SBS /P (P) < (P)  A ; P < P  1
SBS .W (W) < (W)  A
When M is set, include the carry from a previous operation in the subtraction
SBS N (N) < (N)  A + C  1
SBS ,D (PC+1) < D  A + C  1
SBS /P (P) < (P)  A + C  1
SBS /P+ P < P + 1 ; (P) < (P)  A + C  1
SBS /P (P) < (P)  A + C  1 ; P < P  1
SBS .W (W) < (W)  A + C  1
In the immediate mode operation, data ‘D’ is taken from the location (PC+1), ie the word immediately after the opcode, and the the result is returned to that location.
The result of the subtraction passes through the Operand Register as it written to memory.
The accumulator is unchanged by the result of the SBS instruction.
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

0110 
0 
11’b<nonzero addr> 
none 
SBS N 
TBC 

0110 
0 
11’b000000000000 
16’b<data> 
SBS ,D 
TBC 

0110 
1 
x 
x0 
8’b<nonzero ptr> 
none 
SBS /P 
TBC 

0110 
1 
x 
01 
8’b<nonzero ptr> 
none 
SBS /P+ 
TBC 

0110 
1 
x 
11 
8’b<nonzero ptr> 
none 
SBS /P 
TBC 

0110 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
SBS .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
C is cleared if the operation results in a borrow (carry), otherwise set
Z is set if the result is allzeroes, otherwise cleared
S is set if the MSB of the result is a ‘1’, otherwise cleared
V is set if the subtraction of two numbers of different sign results in a number with the same sign as the subtrahend, otherwise cleared
SJM  Switch Jump¶
The contents of the accumulator are added to the contents of the program counter (which has already been incremented to point to the next instruction). If the value of the accumulator is zero then the program will continue execution in sequence.
Note that the MSB of the result is always discarded, so that the program counter value will never exceed the 15b address range of the machine.
Function
SJM PC < PC + 1 + A
Instruction Encoding
Opcode Word 
Function 
Cycle count 

F 

0001 
12’bxxxxxxxxxxxx 
SJM 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
 
 
 
 
The Condition Register is unaffected by the addition in this instruction.
SLA,SLE,SLL,SRA,SRE,SRL  Shift and Rotation¶
These instructions perform single or multilength shifts and rotations of a specified register or memory location.
Several different types of shift are available
SLA  Shift Left Arithmetic
All bits are shifted left by the specified number of places, and the incoming LSBs are filled with ‘0’
SRA  Shift Right Arithmetic
All bits are shifted right by the specified number of places, and the original sign bit is extended to fill the incoming MSBs
SLL  Shift Left Logical
All bits are shifted left by the specified number of places, and the incoming LSBs are filled with ‘0’.
NB This is exactly the same data operation as SLA, but the flags are handled differently (see below)
SRL  Shift Right Logical
All bits are shifted right by the specified number of places, and the incoming MSBs are filled with ‘0’
SLE  Rotate Left (Shift Left Endaround)
All bits are rotated left by the specified number of places, with the MSBs being recirculated into the LSB positions
SRE  Rotate Right (Shift Right Endaround)
All bits are shifted right by the specified number of places, with the LSBs being recirculated into the MSB positions
The data to be shifted can be one of
the Accumulator (A),
the Condition Register (CR), or
a memory location (W)
The shifts will be either single length, if the ‘M’ flag is clear, or double length if ‘M’ is set.
Any shifts where the Condition Register itself is to be shifted will treat that register as a bit pattern and all bits will be left in the shifted state at the end of the instruction.
Single Length Shifts¶
When ‘M’ is clear the bottom 4 LSBs of the Opcode word determine the number of places, n, to shift, ie 0<=n<=15.
In single length operation the data to be shifted can be one of
the Accumulator (A),
the Condition Register (CR), or
a memory location (W)
All singlelength shifting is done through the Operand Register and the result is copied into the required destination at the end of the operation. When a memory location is specified as the source that location is updated at the end of the shift via a readmodifywrite operation. The Accumulator is not modified when shifting the Condition Register or a memory location.
Function
SLL B A A < A << B
SLL B CR CR < CR << B
SLL B W (W) < (W) << B
SLA B A A < A << B
SLA B CR CR < CR << B
SLA B W (W) < (W) << B
SRL B A A < A >>> B
SRL B CR CR < CR >>> B
SRL B W (W) < (W) >>> B
SRA B A A < A >> B
SRA B CR CR < CR >> B
SRA B W (W) < (W) >> B
Instruction Encoding
Opcode Word 
Operand 
Function 
Cycle count 

F 
T 
R 
S 
J 
B 

0000 
00 
x0 
00 
0x 
4’b<shift num> 
none 
SRA B A 
TBC 

0000 
00 
x0 
00 
10 
4’b<shift num> 
none 
SRL B A 
TBC 

0000 
00 
01 
00 
0x 
4’b<shift num> 
none 
SRA B CR 
TBC 

0000 
00 
01 
00 
10 
4’b<shift num> 
none 
SRL B CR 
TBC 

0000 
00 
11 
00 
0x 
4’b<shift num> 
x 
15’b<addr> 
SRA B W 
TBC 
0000 
00 
11 
00 
10 
4’b<shift num> 
x 
15’b<addr> 
SRL B W 
TBC 
0000 
00 
x0 
01 
0x 
4’b<shift num> 
none 
SLA B A 
TBC 

0000 
00 
x0 
01 
10 
4’b<shift num> 
none 
SLL B A 
TBC 

0000 
00 
01 
01 
0x 
4’b<shift num> 
none 
SLA B CR 
TBC 

0000 
00 
01 
01 
10 
4’b<shift num> 
none 
SLL B CR 
TBC 

0000 
00 
11 
01 
0x 
4’b<shift num> 
x 
15’b<addr> 
SLA B W 
TBC 
0000 
00 
11 
01 
10 
4’b<shift num> 
x 
15’b<addr> 
SLL B W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
Shift Type 
 
 
 
x 
 
Arithmetic Shifts 

 
 
 
x 
x 
x 
 
Logical Shifts 
For arithmetic shift operations not specifying the Condition Register:
S is set if the MSB of the shifted data is ‘1’, otherwise cleared
V is set if the MSB of the shifted data is permanently or temporarily different to its original state, ie for multiple place shifts the flag is set if any bit passing through the MSB position is different to the original sign even if the shift finishes with the sign bit apparently unchanged.
C is preserved
Z is meaningless at the end of the instruction
For logical shift operations not specifying the Condition Register:
C is preserved
V, Z and S are meaningless
Single Length Rotations¶
Function
SLE B A A < _rotl(A,B)
SLE B CR CR < _rotl(CR,B)
SLE B W (W) < _rotl((W),B)
SRE B A A < _rotr(A,B)
SRE B CR CR < _rotr(CR,B)
SRE B W (W) < _rotr((W),B)
Instruction Encoding
Opcode Word 
Operand 
Function 
Cycle count 

F 
T 
R 
S 
J 
B 

0000 
00 
x0 
00 
11 
4’b<shift num> 
none 
SRE B A 
TBC 

0000 
00 
01 
00 
11 
4’b<shift num> 
none 
SRE B CR 
TBC 

0000 
00 
11 
00 
11 
4’b<shift num> 
x 
15’b<addr> 
SRE B W 
TBC 
0000 
00 
x0 
01 
11 
4’b<shift num> 
none 
SLE B A 
TBC 

0000 
00 
01 
01 
11 
4’b<shift num> 
none 
SLE B CR 
TBC 

0000 
00 
11 
01 
11 
4’b<shift num> 
x 
15’b<addr> 
SLE B W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
x 
x 
x 
 
For operations not specifying the Condition register:
C is preserved
S, V and Z are meaningless at the end of the instruction
Double Length Shifts¶
When ‘M’ is set, a double length operation is performed on a 32bit word which is made up of the Accumulator in the 16 MSBs and the internal Operand Register providing the lower 16 bits. The Operand Register is either preloaded by a previous instruction (R=0,2) or from a memory location (R=3). When R=3 the least significant word of the result will be written back to the same memory location.
In double length mode the number of bit positions to be shifted is taken from the 5 LSBs of the opcode word. The lower 4 LSBs are the same bit as used in the singlelength mode, but the 5th bit (the MSB) is taken from one of the bit fields used to select between logical, arithmetic and rotate variations. Executing a shift originally assembled as a singlelength operation but with the M flag set to ‘1’ can therefore have unexpected results. For this reason the assembler provides a specific mnemonic for the double length operations ending with a .D suffix. The programmer is responsible for ensuring that the M flag is in the correct state before executing either a single or double length operation.
In double length mode, the rotate operations are undefined.
Function
SLA.D B W {A, (W)} < {A, (W)} << B
SLL.D B W {A, (W)} < {A, (W)} << B
SRA.D B W {A, (W)} < {A, (W)} >> B
SRL.D B W {A, (W)} < {A, (W)} >>> B
SLA.D B A {A, OR} < {A, OR} << B
SLL.D B A {A, OR} < {A, OR} << B
SRA.D B A {A, OR} < {A, OR} >> B
SRL.D B A {A, OR} < {A, OR} >>> B
SLA.D B CR {A, CR} < {A, CR} << B
SLL.D B CR {A, CR} < {A, CR} << B
SRA.D B CR {A, CR} < {A, CR} >> B
SRL.D B CR {A, CR} < {A, CR} >>> B
Instruction Encoding
Opcode Word 
Operand 
Function 
Cycle count 

F 
T 
R 
S 
J 
B 

0000 
00 
x0 
00 
0 
5’b<shift num> 
none 
SRA.D B A 
TBC 

0000 
00 
x0 
00 
1 
5’b<shift num> 
none 
SRL.D B A 
TBC 

0000 
00 
x0 
01 
0 
5’b<shift num> 
none 
SLA.D B A 
TBC 

0000 
00 
x0 
01 
1 
5’b<shift num> 
none 
SLL.D B A 
TBC 

0000 
00 
10 
00 
0 
5’b<shift num> 
none 
SRA.D B CR 
TBC 

0000 
00 
10 
00 
1 
5’b<shift num> 
none 
SRL.D B CR 
TBC 

0000 
00 
10 
01 
0 
5’b<shift num> 
none 
SLA.D B CR 
TBC 

0000 
00 
10 
01 
1 
5’b<shift num> 
none 
SLL.D B CR 
TBC 

0000 
00 
11 
00 
0 
5’b<shift num> 
X 
15’b <addr> 
SRA.D B W 
TBC 

0000 
00 
11 
00 
1 
5’b<shift num> 
X 
15’b <addr> 
SRL.D B W 
TBC 

0000 
00 
11 
01 
0 
5’b<shift num> 
X 
15’b <addr> 
SLA.D B W 
TBC 

0000 
00 
11 
01 
1 
5’b<shift num> 
X 
15’b <addr> 
SLL.D B W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
Shift Type 
 
 
 
x 
 
Arithmetic Shifts 

 
 
 
x 
x 
x 
 
Logical Shifts 
For arithmetic shift operations not specifying the Condition Register:
S is set if the MSB of the shifted data is ‘1’, otherwise cleared
V is set if the MSB of the shifted data is permanently or temporarily different to its original state, ie for multiple place shifts the flag is set if any bit passing through the MSB position is different to the original sign even if the shift finishes with the sign bit apparently unchanged.
C is preserved
Z is meaningless at the end of the instruction
For logical shift operations not specifying the Condition Register:
C is preserved
V, Z and S are meaningless
STO  Store Accumulator to Memory¶
Store the value in the accumulator to the specified memory location
Function
STO N (N) < A
STO ,D (PC+1) < A
STO /P (P) < A
STO /P+ P < P + 1 ; (P) < A
STO /P (P) < A ; P < P  1 ;
STO .W (W) < A
The operand register (OR) will have the same value as the accumulator at the end of this instruction.
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

0100 
0 
11’b<nonzero addr> 
none 
STO N 
TBC 

0100 
0 
11’b000000000000 
16`b<data> 
STO ,D 
TBC 

0100 
1 
x 
x0 
8`b<nonzero ptr> 
none 
STO /P 
TBC 

0100 
1 
x 
01 
8`b<nonzero ptr> 
none 
STO /P+ 
TBC 

0100 
1 
x 
11 
8`b<nonzero ptr> 
none 
STO /P 
TBC 

0100 
1 
x 
xx 
8`b00000000 
x 
15`b<addr> 
STO .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
0 
 
Z is set if the accumulator value is allzeroes, otherwise cleared
S is set if the MSB of the accumulator is a ‘1’, otherwise cleared
V is always cleared
SUB  Subtract (With Carry)¶
Perform either a single or multi length substraction of the accumulator from the value of a provided operand depending on the state of the multilength flag ‘M’ in the condition register.
Function
When M is clear, perform a simple subtraction
SUB N A < (N)  A
SUB ,D A < D  A
SUB /P A < (P)  A
SUB /P+ P < P + 1 ; A < (P)  A
SUB /P A < (P)  A ; P < P  1
SUB .W A < (W)  A
When M is set, include the carry from a previous operation in the subtraction
SUB N A < (N)  A + C  1
SUB ,D A < D  A + C  1
SUB /P A < (P)  A + C  1
SUB /P+ P < P + 1 ; A < (P)  A + C  1
SUB /P A < (P)  A + C  1 ; P < P  1
SUB .W A < (W)  A + C  1
Instruction Encoding
Opcode Word 
Operand Word 
Function 
Cycle count 

F 
I 
N 

R 
P 

1010 
0 
11’b<nonzero addr> 
none 
SUB N 
TBC 

1010 
0 
11’b000000000000 
16’b<data> 
SUB ,D 
TBC 

1010 
1 
x 
x0 
8’b<nonzero ptr> 
none 
SUB /P 
TBC 

1010 
1 
x 
01 
8’b<nonzero ptr> 
none 
SUB /P+ 
TBC 

1010 
1 
x 
11 
8’b<nonzero ptr> 
none 
SUB /P 
TBC 

1010 
1 
x 
xx 
8’b00000000 
x 
15’b<addr> 
SUB .W 
TBC 
Condition Register
F 
M 
C 
S 
V 
Z 
I 
 
 
 
C is cleared if the operation results in a borrow (carry), otherwise set
Z is set if the result is allzeroes, otherwise cleared
S is set if the MSB of the result is a ‘1’, otherwise cleared
V is set if the subtraction of two numbers of different sign results in a number with the same sign as the subtrahend, otherwise cleared